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VLSI CAD Part II: Layout

VLSI CAD Part II: Layout

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9.0/10 (Our Score)
Product is rated as #1 in category Computer-Aided Design (CAD)

You should complete the VLSI CAD Part I: Logic course before beginning this course. A modern VLSI chip is a remarkably complex beast: billions of transistors, millions of logic gates deployed for computation and control, big blocks of memory, embedded blocks of pre–designed functions designed by third parties (called “intellectual property” or IP blocks). How do people manage to design these complicated chips? Answer: a sequence of computer aided design (CAD) tools takes an abstract description of the chip, and refines it step–wise to a final design. This class focuses on the major design tools used in the creation of an Application Specific Integrated Circuit (ASIC) or System on Chip (SoC) design. Our focus in this part of the course is on the key logical and geometric representations that make it possible to map from logic to layout, and in particular, to place, route, and evaluate the timing of large logic networks. Our goal is for students to understand how the tools themselves work, at the level of their fundamental algorithms and data structures. Topics covered will include: technology mapping, timing analysis, and ASIC placement and routing. Recommended Background: Programming experience (C, C++, Java, Python, etc.) and basic knowledge of data structures …

Instructor Details

Rob A. Rutenbar is an Adjunct Professor of Computer Science at the University of Illinois at Urbana-Champaign. He received his PhD from the University of Michigan in 1984, and spent the next 25 years on the faculty at Carnegie Mellon University. He joined Illinois in 2010 as the Head of the Computer Science Department. He has worked on design tools for integrated circuits for the last 30 years, in areas ranging from synthesis, to optimization, to formal verification, simulation, and geometric layout. On a leave of absence from CMU in 1998, he cofounded Neolinear Inc. to commercialize the first successful tools for analog circuit design; he served as Neolinear’s Chief Scientist until its acquisition by Cadence (NASDAQ: CDNS) in 2004. His research spans both chip design methods and custom silicon chip architectures. In 2017 he was appointed Senior Vice Chancellor for Research at the University of Pittsburgh, where he also holds faculty appointments in both Computer Science and Electrical and Computer Engineering. Prof. Rutenbar has won many awards for his work. He is a Fellow of the IEEE and the ACM. He received the 2001 Semiconductor Research Corporation Aristotle Award in recognition of the impact of his teaching and his students on the US semiconductor industry. He received the 2007 IEEE CAS Industrial Pioneer Award for his contributions to making circuit synthesis tools a commercial success. Most recently, he won the 2013 IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award for work predicting nanoscale chip variations using techniques from machine learning and Bayesian statistics.

Specification: VLSI CAD Part II: Layout

Duration

12 hours

Year

2017

Level

Intermediate

Certificate

Yes

Quizzes

Yes

19 reviews for VLSI CAD Part II: Layout

4.9 out of 5
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  1. BHARATH K

    Amazing!!!

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  2. Kanishka S

    Excellent course, very helpful!

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  3. Pankaj M

    Very good to learn algorithms!

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  4. Mohammad H

    It was a great experience, really great lecturer without exaggerating, but the programming assignment 3 (which is optional) was totally a nightmare, I wrote about 1000 line of code to do both the essential and the extra parts, but not yet. I hope there was another course for design using HDL like Verilog or System Verilog.

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  5. Akash L

    Great basic overview of the core design principles for EDA

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  6. Robin M

    As a software developer without background in EE I have always wondered how Boolean logic is turned into actual physical hardware, and this course (along with its predecessor “VLSI CAD Part I: Logic”) has answered all my questions.

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  7. Shaanvi M

    very helpful, and delivered very well.

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  8. Navdeep D

    Good

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  9. V V R R

    THANK YOU

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  10. K L N A

    EXCELLENT

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  11. Arvind

    no comments

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  12. HARSH V P

    excelllent

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  13. Shresth N

    very nice and challenging

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  14. Arighna D

    Excellent.

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  15. Divyang T

    A very good course for students who want to have an understanding of Physical Design process in semiconductor industry. I want to thank professor for making this course so informative. A must for people looking to dive deep into Electronics.

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  16. kanishk j

    Good course content and prof. ‘s teaching method makes it easy to comprehend quite quickly.

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  17. Md. F K

    Another interesting and well taught course.

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  18. Devansh S

    An awesome course which I can put to great use in my academic life.

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  19. SIDDEM M

    good

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